ENGINEER TRAINEE

SmartDV Technologies India Private Limited 

• Experience 0 to 2 yrs
• Salary As per Industry Standards
• Location Bengaluru/ Bangalore
• Key Skills C or C++ Verilog or VHDL or SystemVerilog Digital design
• Job Function IT/Telecom - Software
• Industry Banking
• Specialization Software Engineer
• Qualification:
  • ME/ M.Tech./ MS (Engg/ Sciences)
  • BE/ B.Tech (Engineering)

Job Description

• B.E or MTech from reputed university with 0-2 years experience.
• Strong understanding of Digital design
• Working experience with Verilog or VHDL or SystemVerilog
• Experience in writing C or C++
• Understanding of OOPS.
• Knowledge of Perl or Python or TCL scripting languages
• Very good academic track record

Job Posted by

• Company: SmartDV Technologies India Private Limited

SmartDV was started by Durga Lakshmi Sangisetti, Deepak Kumar Tala and Kavitha Tala. Together we have more than 40 years experience in design and verification of complex ASIC's. We maintain our leadership by continuously staying atop the latest technology advances and bringing that information to our customers. Our biggest strength is ability to automate writing of verification environment and testcases for ASIC verification to save huge time it takes to verify ASIC's. SmartDV offers industry standard design and Verification IP like I2C, ethernet, lin, Flexray, SATA, SAS, SPI, Fiber Channel, OCP, MIPI CSI, MIPI DSI, MIPI RFFE, MIPI HSI, MIPI Unipro, MIPI SlimBus, MIPI M-PHY, MIPI D-PHY and, MIPI SPMI in SystemVerilog. We can offer IIP's and VIP's in any language (SystemVerilog, Verilog, OpenVera, E, SystemC). SmartDV offers design and verification services in the area of ASIC and FPGA design, with emphasis on quality deliverable. Our offerings are designed to function with minimal customer involvement and, the process ensures flawless and timely delivery be it designs starting from specifications or point services.